1. Field of the Invention
The present invention generally relates to data transmission, and in particular to signal estimation in the presence of distortion such as intersymbol interference (ISI).
2. Description of the Related Art
There has been proposed Delayed decision-feedback sequence estimation (DDFSE), which is a method of estimating the distorted signals, in "Delayed Decision Feedback Sequence Estimation" by A. Duel-Hallen and C. Heegard (IEEE Transactions on communications, pp 428-436, Vol. 37, No. 5, May 1989). DDFSE is an estimation algorithm that would reduce computational complexity with only slight degradation in the quality of signal estimation compared with MLSE (maximum-likelihood sequence estimation) in digital communications over intersymbol interference channels.
As another method for estimating the distorted signals, the inventor has proposed an adaptive reduced-state sequence estimation in NEC Research & Development (pp 188-194, Vol. 35, No. 2, April 1994). the adaptive reduced-state sequence estimation (RSSE) uses a memory table to estimate both linearly and nonlinearly distorted signals with employing a loop configuration for feedback of estimated data.
In a signal estimator employing the feedback loop configuration as described above, it is necessary to complete a set of computations within a time period of a symbol. More specifically, as shown in FIG. 1, the estimator performs three kinds of computations, that is, generation of estimated signals, generation of branch metrics, and comparison for path metric selection, within the time period of Ts. In the case of a Viterbi algorithm having no loop therein, pipeline processing can be employed to achieve high-speed computation. However, since the signal estimator uses estimated data one symbol before for calculation of the subsequent symbol, the pipeline processing cannot be employed.
Therefore, to achieve high-speed computation, the signal estimator needs a high-speed arithmetic circuit which increases in consumption power, providing a tradeoff between speed and power consumption.